This invention relates to semiconductor device fabrication processes. More specifically, the invention relates to plasma-based chemical vapor deposition and etch processes for forming dielectric layers, particularly in high aspect ratio, narrow width recessed features.
It is often necessary in semiconductor processing to fill high aspect ratio gaps with insulating material. This is the case for shallow trench isolation, inter-metal dielectric layers, passivation layers, etc. As device geometries shrink and thermal budgets are reduced, void-free filling of narrow width, high aspect ratio spaces (e.g., AR>3:1) becomes increasingly difficult due to limitations of existing deposition processes.
Most deposition methods either deposit more material on the upper region than on the lower region of a side-wall or form cusps at the entry of the gap. As a result the top part of a high aspect ratio structure sometimes closes prematurely leaving voids within the gap's lower portions. This problem is exacerbated in small features. Furthermore, as aspect ratios increase, the shape of the gap itself can contribute to the problem. High aspect ratio gaps often exhibit reentrant features, which make gap filling even more difficult. The most problematic reentrant feature is a narrowing at the top of the gap; the etched side-walls slope inward near the top of the gap. For a given aspect ratio feature, this increases the ratio of gap volume to gap access area seen by the precursor species during deposition. Hence voids and seams become even more likely.
The deposition of silicon dioxide assisted by high-density plasma chemical vapor deposition (HDP CVD)—a directional (bottom-up) CVD process—has become the preferred method for high aspect ratio gap fill. The method deposits more material at the bottom of a high aspect ratio structure than on its sidewalls. It accomplishes this by directing charged dielectric precursor species downward, to the bottom of the gap. Thus, HDP CVD is not an entirely diffusion-based (isotropic) process.
A gap fill technique which involves a sequence of deposition, etch and deposition steps using an HDP reactor has been developed to maintain the cusp opening wide enough for a subsequent deposition(s) to completely fill the gap. Such HDP deposition-etch-deposition (“dep-etch-dep”) processes are described, for example, in U.S. Pat. Nos. 6,335,261 and 6,030,881, the disclosures of which are incorporated herein by reference for all purposes.
The etch component of these dep-etch-dep processes typically uses a fluorine-based etchant, in particular NF3, and is isotropic. The etch process is susceptible to a “loading effect,” such that etch process response on each successive wafer processed in a reactor is a function of the loading condition of the reactor. “Loading,” in this instance, refers to gap fill material that builds up on chamber components, particularly the chamber sidewalls, over successive deposition processes. This “loading effect” phenomena leads to a wafer-to-wafer process repeatability issue with dep-etch-dep processes thus limiting the proliferation of this technique despite its superior gap fill capability.
Accordingly, a dep-etch-dep process with wafer-to-wafer repeatability and without a redeposition or loading effect problem would be desirable.